#ifndef _ARM32INSNDECODER_H_
#define _ARM32INSNDECODER_H_

#include <stdint.h>
#include <stdio.h>
#include <vector>
#include "bitutils.h"

typedef std::vector<uint8_t> ByteVector;
union shifter {
    struct {
        unsigned imm8:8;
        unsigned rot:4;
    } imm;      // bit 25 (I) == 1
    struct {
        unsigned Rm:4;
        unsigned eq0:1;
        unsigned type:2;
        unsigned shift:5;
    } shift;
    struct {
        unsigned Rm:4;
        unsigned eq1:1;
        unsigned type:2;
        unsigned eq0:1;
        unsigned Rs:4;
    } regshift;
};
struct  scaledreg{
    unsigned Rm:4;
    unsigned eq0:1;
    unsigned type:2;
    unsigned shift:5;
};

union arm32bits {
    struct {
        unsigned shifter:12;
        unsigned Rd:4;
        unsigned Rn:4;
        unsigned s:1;
        unsigned opc:4;
        unsigned i:1;
        unsigned eq0:2;
        unsigned cc:4;
    } dp;
    struct {
        unsigned regindex:12;
        unsigned Rd:4;
        unsigned Rn:4;
        unsigned l:1;
        unsigned w:1;
        unsigned b:1;
        unsigned u:1;
        unsigned p:1;
        unsigned i:1;
        unsigned eq1:2;
        unsigned cc:4;
    } ldst;
    struct {
        int ofs:24;
        unsigned l:1;
        unsigned eq5:3;
        unsigned cc:4;
    } branch;
    struct {
        unsigned imml:4;
        unsigned eq7:4;
        unsigned immh:12;
        unsigned eqE12:12;
    } bkpt;
    struct {
        int ofs:24;
        unsigned h:1;
        unsigned eq7D:7;
    } blximm;
    struct {
        unsigned Rm:4;
        unsigned eq4BFFC:22;
        unsigned type:2;        // 0:? 1:bx, 2:bxj 3:blx
        unsigned cc:4;
    } blxreg;
    // ldc ?
    struct {
        unsigned list:16;
        unsigned Rn:4;
        unsigned l:1;
        unsigned w:1;
        unsigned special:1;
        unsigned u:1;
        unsigned p:1;
        unsigned eq4:3;
        unsigned cc:4;
    } ldmstm;
    struct {
        unsigned amodel:4;      // or Rm
        unsigned eq1a:1;
        unsigned h:1;
        unsigned s:1;
        unsigned eq1b:1;
        unsigned amodeh:4;
        unsigned Rd:4;
        unsigned Rn:4;
        unsigned l:1;
        unsigned w:1;
        unsigned i:1;
        unsigned u:1;
        unsigned p:1;
        unsigned eq0:3;
        unsigned cc:4;
    } ldrx;
};
enum dp_opcodes {
   DPOPC_AND, DPOPC_EOR, DPOPC_SUB, DPOPC_RSB, DPOPC_ADD, DPOPC_ADC, DPOPC_SBC, DPOPC_RSC, DPOPC_TST, DPOPC_TEQ, DPOPC_CMP, DPOPC_CMN, DPOPC_ORR, DPOPC_MOV, DPOPC_BIC, DPOPC_MVN
};
class instruction {
public:
    class regcallback {
        public:
        virtual unsigned use(unsigned nr) const=0;
        virtual unsigned def(unsigned nr) const=0;
    };
    class usedefcallback : public regcallback {
        instruction& _decoder;
        public:
        usedefcallback(instruction& decoder) : _decoder(decoder) { }
        virtual unsigned use(unsigned nr) const
        {
            _decoder.use(nr);
            return nr;
        }
        virtual unsigned def(unsigned nr) const
        {
            _decoder.def(nr);
            return nr;
        }
    };
    class replacecallback : public regcallback {
        unsigned _oldnr;
        unsigned _newnr;
        public:
        replacecallback(unsigned oldnr, unsigned newnr) : _oldnr(oldnr), _newnr(newnr) { }
        virtual unsigned use(unsigned nr) const
        {
            if (nr==_oldnr)
                return _newnr;
            return nr;
        }
        virtual unsigned def(unsigned nr) const
        {
            if (nr==_oldnr)
                return _newnr;
            return nr;
        }
    };

    instruction(uint8_t *code, int size)
        : _insn(*(arm32bits*)code), _branch(false), _used(0), _defined(0)
    {
printf("decoding b=%d %08lx\n", sizeof(arm32bits), opcode());
        process_usedef(usedefcallback(*this));
    }

    void process_usedef(const regcallback& cb)
    {
//printf("ldrx: %d %d %d\n", _insn.ldrx.eq0==0, _insn.ldrx.eq1a==1, _insn.ldrx.eq1b==1);
//printf("dp: %d\n", _insn.dp.eq0==0);
//printf("ldst: %d\n", _insn.ldst.eq1==1);
//printf("branch: %d\n", _insn.branch.eq5==5);
//printf("bkpt: %d %d\n", _insn.bkpt.eq7==7, _insn.bkpt.eqE12==0xE12);
//printf("blximm: %d\n", _insn.blximm.eq7D==0x7D ) ;
//printf("blxreg: %d %d\n", _insn.blxreg.eq4BFFC==0x4BFFC, _insn.blxreg.type!=0);
//printf("ldmstm: %d\n", _insn.ldmstm.eq4==4);


        // note: this gives warning 'conditional expr is constant' due to the '0'
        if (0
    || (_insn.ldrx.eq0==0 && _insn.ldrx.eq1a==1 && _insn.ldrx.eq1b==1 && handle_miscsldr(cb)) 
    || (_insn.dp.eq0==0 && handle_dataprocessing(cb)) 
    || (_insn.ldst.eq1==1 && handle_loadstore(cb))
    || (_insn.branch.eq5==5 && handle_branch(cb))
    || (_insn.bkpt.eq7==7 && _insn.bkpt.eqE12==0xE12 && handle_breakpoint(cb))
    || (_insn.blximm.eq7D==0x7D && handle_blximm(cb)) 
    || (_insn.blxreg.eq4BFFC==0x4BFFC && _insn.blxreg.type!=0 && handle_blxreg(cb))
    || (_insn.ldmstm.eq4==4 && handle_ldmstm(cb))
           ) {
            printf("instruction decoded: b=%d use=%04x, def=%04x\n", _branch, _used, _defined);
        }
        else {
            printf("unknown instruction\n");
        }
    }

private:
    arm32bits _insn;
    bool _branch;
    uint32_t _used;
    uint32_t _defined;



bool handle_dataprocessing(const regcallback& cb)
{
    printf("handle_dataprocessing\n");
    // ADD Rd, Rm, Rn
    // SUB Rd, Rm, Rn
    // MOV Rd, Rm

    if (_insn.dp.opc<DPOPC_TST || _insn.dp.opc==DPOPC_ORR || _insn.dp.opc==DPOPC_BIC)
    {
        _insn.dp.Rd= cb.def(_insn.dp.Rd);
        _insn.dp.Rn= cb.use(_insn.dp.Rn);
        if (!_insn.dp.i) {
            unsigned sh= _insn.dp.shifter;
            use_shifter(cb, sh);
            _insn.dp.shifter= sh;
        }
    }
    else if (_insn.dp.opc<DPOPC_ORR)
    {
        if (_insn.dp.Rd)
            return false;
        _insn.dp.Rn= cb.use(_insn.dp.Rn);
        if (!_insn.dp.i) {
            unsigned sh= _insn.dp.shifter;
            use_shifter(cb, sh);
            _insn.dp.shifter= sh;
        }
    }
    else if (_insn.dp.opc==DPOPC_MOV || _insn.dp.opc==DPOPC_MVN) {
        _insn.dp.Rd= cb.def(_insn.dp.Rd);
        if (_insn.dp.Rn)
            return false;
        if (!_insn.dp.i) {
            unsigned sh= _insn.dp.shifter;
            use_shifter(cb, sh);
            _insn.dp.shifter= sh;
        }
    }
    else {
        throw "decode error";
    }
    return true;
}
bool handle_loadstore(const regcallback& cb)
{
    printf("handle_loadstore\n");
    if (_insn.ldst.l) { // load
        _insn.ldst.Rd= cb.def(_insn.ldst.Rd);
    }
    else { // store
        _insn.ldst.Rd= cb.use(_insn.ldst.Rd);
    }
    _insn.ldst.Rn= cb.use(_insn.ldst.Rn);
    if (_insn.ldst.w==_insn.ldst.p) {
        // pre/post indexed
        _insn.ldst.Rn= cb.def(_insn.ldst.Rn);
    }
    if (_insn.ldst.i) {
        unsigned ri= _insn.ldst.regindex;
        if (use_amode(cb, ri)) {
            _insn.ldst.regindex= ri;
            return true;
        }
        else {
            return false;
        }
    }

    //ipubwl
    //0.....   imm offset/index
    //1.....  sh=0 : reg ofs/index
    //1.....  scaled reg ofs/index
    //
    // p=0 w=0: post index
    // p=0 w=1: 't' variant
    // p=1 w=0: offs 
    // p=1 w=1: pre index
    // u=0 : substract from base
    // u=1 : add to base
    // b=0 : word
    // b=1 : byte
    //
    //01..0.  imm offset
    //11..0.  (scaled )reg ofs
    //01..1.  imm preindexed  [..]!
    //11..1.  (scaled)reg preindexed  [..]!
    //00..0.  imm post indexed  [],..
    //10..0.  (scaled) reg post indexed  [],..
    return true;
}
bool handle_branch(const regcallback& cb)
{
    printf("handle_branch\n");
    _branch= true;
    return true;
}
bool handle_blximm(const regcallback& cb)
{
    printf("handle_blximm\n");
    _branch= true;
    return true;
}
bool handle_blxreg(const regcallback& cb)
{
    printf("handle_blxreg\n");
    _insn.blxreg.Rm= cb.use(_insn.blxreg.Rm);
    return true;
}

bool handle_breakpoint(const regcallback& cb)
{
    printf("handle_breakpoint\n");
    return true;
}
bool handle_ldmstm(const regcallback& cb)
{
    printf("handle_ldmstm\n");
    _insn.ldmstm.Rn= cb.use(_insn.ldmstm.Rn);
    if ((_insn.ldmstm.special && !(_insn.ldmstm.list&0x8000)) || _insn.ldmstm.w) {
        if (_insn.ldmstm.w)
            _insn.ldmstm.Rn= cb.def(_insn.ldmstm.Rn);
    }
    unsigned regs= _insn.ldmstm.list;
    handle_reglist(cb, regs, _insn.ldmstm.l);
    _insn.ldmstm.list= regs;

    return true;
}
bool handle_miscsldr(const regcallback& cb)
{
    printf("handle_miscsldr\n");
    bool store=false;
    bool dbl=false;
    switch(_insn.ldrx.l*4+_insn.ldrx.s*2+_insn.ldrx.h)
    {
        case 0: throw "decoder error";
        case 1: store= true; break; // strh
        case 2: dbl=true;break; // ldrd
        case 3: dbl=true; store=true; break; // strd
        case 4: throw "decoder error";
        case 5: break; // ldrh
        case 6: break; // ldrsb
        case 7: break; // ldrsh
    }
    _insn.ldrx.Rn= cb.use(_insn.ldrx.Rn);
    if (store)
        _insn.ldrx.Rd= cb.use(_insn.ldrx.Rd);
    else
        _insn.ldrx.Rd= cb.def(_insn.ldrx.Rd);
    if (!_insn.ldrx.i)
        _insn.ldrx.amodel= cb.use(_insn.ldrx.amodel);
    if (dbl) {
        if (store)
            cb.use(_insn.ldrx.Rd+1);
        else
            cb.def(_insn.ldrx.Rd+1);
        // todo: STRD R14,R15  cannot be changed into  STRD R14,R0
        //   but should be changed in 2 seperate store insns
    }
    if (_insn.ldrx.p==_insn.ldrx.w)
        _insn.ldrx.Rn= cb.def(_insn.ldrx.Rn);
    return true;
}
bool use_amode(const regcallback& cb, unsigned& ribits)
{
    scaledreg ri= int2bf<scaledreg>(ribits);
    if (ri.eq0)
        return false;
    ri.Rm= cb.use(ri.Rm);
    ribits= bf2int(ri);
    return true;
}
void use_shifter(const regcallback& cb, unsigned& shbits)
{
    shifter sh= int2bf<shifter>(shbits);
    if (sh.regshift.eq0==0 && sh.regshift.eq1==1) {
        sh.regshift.Rs= cb.use(sh.regshift.Rs);
        sh.regshift.Rm= cb.use(sh.regshift.Rm);
        shbits= bf2int(sh);
    }
    else if (sh.shift.eq0==0) {
        sh.regshift.Rm= cb.use(sh.regshift.Rm);
        shbits= bf2int(sh);
    }
    else
        throw "decoder error";
}
void handle_reglist(const regcallback& cb, unsigned& list, bool def)
{
    int orglist= list;
    for (int r=0 ; r<16 ; r++)
    {
        if (orglist&1) {
            int tmpr= def ? cb.def(r) : cb.use(r);
            if (tmpr!=r) {
                list &= ~(1<<r);
                list |= (1<<tmpr);
            }
        }
        orglist>>=1;
    }
}

public:
bool isbranch()
{
    return _branch;
}
void set_relative(int ofs)
{
    _insn.branch.ofs= ofs;
}
int branchofs()
{
    return _insn.branch.ofs;
}

uint32_t opcode()
{
    return bf2int(_insn);
}

void replace_reg(int origr, int newr)
{
    process_usedef(replacecallback(origr, newr));
}
void use(int regnr)
{
    _used |= (1<<regnr);
}
void def(int regnr)
{
    _defined |= (1<<regnr);
}
uint32_t used()
{
    return _used;
}
uint32_t defined()
{
    return _defined;
}
bool used(int nr)
{
    return (_used>>nr)&1;
}
bool defined(int nr)
{
    return (_defined>>nr)&1;
}

};
#endif